{"id":11848,"date":"2023-07-03T11:48:25","date_gmt":"2023-07-03T11:48:25","guid":{"rendered":"https:\/\/dgzx.hk?p=11848"},"modified":"2023-07-03T11:49:48","modified_gmt":"2023-07-03T11:49:48","slug":"the-implementation-of-ov7620","status":"publish","type":"post","link":"https:\/\/dgzx.hk\/ja\/the-implementation-of-ov7620\/","title":{"rendered":"The implementation of ov7620"},"content":{"rendered":"

1. Function control of OV7620<\/span><\/p>\n

The OV7620 is controlled using the SeriaICameraControlBus (SCCB) protocol.<\/span> SCCB is a simplified I2C protocol, SIO-l is a serial clock input line, SIO-O is a serial bidirectional data line, respectively equivalent to SCL and SDA of I2C protocol.<\/span> The bus timing of SCCB is basically the same as that of I2C, and its response signal ACK is called the 9th bit of a transmission unit, which is divided into Don't Care and NA.<\/span> The Don 'tcare bit is generated by the slave machine.<\/span> The NA bit is generated by the host. Since SCCB does not support multi-byte read and write, the NA bit must be high.<\/span> In addition, SCCB has no concept of repeated start, so in the SCCB read cycle, the host must send the bus stop condition after sending the on-chip register address.<\/span> Otherwise, the slave will not be able to generate a Don 'tCare response signal when the read command is sent.<\/span><\/p>\n

<\/span><\/p>\n

Due to some subtle differences between I2C and SCCB, the SCCB bus is simulated by GPIO.<\/span> The pins connected to SCL are always set to output mode, while the pins connected to SDA dynamically change the input\/output mode of the pins during data transmission by setting the value of IODIR.<\/span> The write cycle of SCCB directly uses the write cycle timing of I2C bus protocol.<\/span> The SC-CB read cycle adds a bus stop condition.<\/span><\/p>\n

<\/span><\/p>\n

The addresses of the OV7620 function registers are 0x00 ~ 0x7C (many of them are reserved registers).<\/span> By setting the corresponding registers, the OV7620 can be made to work in different modes.<\/span> For example, to set OV7620 to continuous scanning and RGB raw data 16-bit output mode, you need to perform the following Settings:<\/span><\/p>\n

<\/span><\/p>\n

I2CSendByte () is a register write function, its first parameter OV7620 is the chip address 0x42 defined by the macro, the second parameter is the on-chip register address, and the third parameter is the corresponding register setting value.<\/span><\/p>\n

<\/span><\/p>\n

2. OV7620 clock synchronization<\/span><\/p>\n

The OV7620 has four synchronization signals: VSYNC (vertical synchronization signal), FODD (odd-field synchronization signal), HSYNC (horizontal synchronization signal) and PCLK (pixel synchronization signal).<\/span> When continuous scanning is adopted, only three synchronization signals, VSYNC, HSYNC and PCLK, are used, as shown in Figure l.<\/span> The HREF level reference signal is also introduced to detect the effective size of the OV7620 scan window.<\/span><\/p>\n

<\/span><\/p>\n

The three external interrupt pins of the LPC2210 are used as inputs to the three synchronization signals, and the corresponding interrupt service programs are Vsync_IRQ (), Hsync_IRQ (), and Pclk_IRQ ().<\/span> A two-dimensional array is defined in memory to store image data, and one dimension is represented by variable y, which is used for horizontal synchronization signal counting.<\/span> Two dimensions are represented by variable x, which is used for pixel synchronization signal counting.<\/span> The basic process of image acquisition is as follows: after OV7620 is initialized with SCCB, enable the corresponding interrupt of VSYNC, and determine whether a frame of data has been obtained in the interrupt service program of Vsync_IRQ ().<\/span> If so, the data is processed in the cycle body of the main program.<\/span> If not, enable the interrupt corresponding to HSYNC and set y to O.<\/span> In the Hsync_IRQ () interrupt service program, determine the valid level of the HREF. If it is valid, y is increased by 1, x is set to O, and the interrupt corresponding to PCLK is enabled.<\/span> In the Pclk_IRQ () interrupt service program, the valid level of the HREF is determined, and if it is valid, the z is increased, and the image data of a pixel is collected.<\/span><\/p>\n

<\/span><\/p>\n

3, image data output speed matching<\/span><\/p>\n

Among the three synchronization signals of OV7620, PCLK has the shortest period.<\/span> When the OV7620 uses a 27MHz system clock, the default PCLK cycle is 74ns.<\/span> The interrupt response time of LPC2210 is much greater than this value.<\/span> The maximum interrupt delay of LPC2210 is 27 processor instruction cycles, the minimum delay is 4 instruction cycles, plus the interrupt service time, the field recovery time, etc., the time to complete an interrupt response is greater than 7 to 30 instruction cycles.<\/span> When the LPC2210 uses the maximum system frequency of 60MHz, its interrupt response time is much higher than that of O. 2 ~ 0, 6\u03bcs, so the PCLK of OV7620 can only be reduced.<\/span> By setting the clock frequency control register, the period of PCLK can be set to about 4\u03bcs.<\/span><\/p>\n

<\/span><\/p>\n

4. Access of image data<\/span><\/p>\n

When the OV7620 is operating in master device mode, its YUV channel will continuously output data to the bus.<\/span> If the YUV channel of OV7620 is directly connected to the DO ~ D15 data bus of LPC2210, the data bus will be interfered with, so that LPC2210 can not run normally;<\/span> If the method of using 74HC244 and other isolation and time-sharing data bus will greatly reduce the running speed of the system, so that LPC2210 can not take the data on the bus in time, resulting in incomplete image data.<\/span> Since the data bus width of LPC2210 is 32 bits, and Flash and SRAM only occupy the low 16-bit data line D0 ~ D15, the method in Figure l can be used to set the idle high 16-bit data line D16 ~ D31 as GPIO for collecting the 16-bit image data output from OV7620.<\/span><\/p>\n

<\/span><\/p>\n

5. Recovery of image data<\/span><\/p>\n

When OV7620 adopts 16-bit output mode, the data output formats of Y channel and UV channel are listed in Table l.<\/span> As you can see from Table l, each row of Y channels and UV channels alternately outputs duplicate data from the previous row and new data from this row.<\/span> Within a row, B data appears only in odd columns and R data appears only in even columns.<\/span><\/p>\n

<\/span><\/p>\n

The following takes a 5\u00d75 pixel lattice as an example to introduce the recovery of image data in detail.<\/span><\/p>\n

<\/span><\/p>\n

First, define a 5\u00d715 byte array to read 5\u00d75 pixel image data in Pclk_IRQ () interrupt service program;<\/span> Then the image data is interpolated, and the odd points are stored in the three consecutive bytes of the array B, G, 0, and the even points are stored in O, G, R;<\/span> Finally, the RGB value of the current row can be calculated by averaging each byte of the current row with each byte of the corresponding column of the next row.<\/span> In each row, the R data of odd-numbered points and the B data of even-numbered points can be obtained by averaging the R and B data of the two points on either side.<\/span><\/p>\n

<\/span><\/p>\n

In this way, an image is restored.<\/span> It can be directly saved into binary files (this system uses serial port output to PC for display), or add BMP bitmap file header information and save into DIB bitmap file with biBitCouNt=24;<\/span> LPC2210 can also be used for further processing of this image data, such as fingerprint recognition.<\/span><\/p>\n

<\/span><\/p>\n

Ov7620 hardware connection<\/span><\/p>\n

The Ov7620 has 16 pins<\/span><\/p>\n

<\/span><\/p>\n

Here's what they mean<\/span><\/p>\n

<\/span><\/p>\n

Gray signal output interface Y0-Y7<\/span><\/p>\n

<\/span><\/p>\n

SCCB Data interface SDA<\/span><\/p>\n

<\/span><\/p>\n

SCCB Data Clock SCL<\/span><\/p>\n

<\/span><\/p>\n

Line interrupt signal HREF<\/span><\/p>\n

<\/span><\/p>\n

Field interrupt signal VSYN<\/span><\/p>\n

<\/span><\/p>\n

Operating voltage 5V vcc<\/span><\/p>\n

<\/span><\/p>\n

Pixel synchronization Signal PCLK (also known as TCLK)<\/span><\/p>\n

<\/span><\/p>\n

Operating voltage 0V<\/span><\/p>\n

<\/span><\/p>\n

Analog signal output interface VTO<\/span><\/p>\n

<\/span><\/p>\n

Of these 16 pins, you need to connect the "operating voltage 5V" to the positive of the power supply, and the "operating voltage 0V" to the ground of the power supply.<\/span> This must not be reversed!!<\/span> Or burn the camera!<\/span> Then the analog signal output interface VTO and the power supply of the ground two wires connected to the TV, you can use the lotus head, or any two wires connected to the TV video input can be.<\/span> This is when the TV can produce pictures.<\/span><\/p>\n

<\/span><\/p>\n

Here only explains the pins that may be needed, the analog camera is nothing more than these signals, it is important that the signal line of the analog camera needs to be separated, which will of course bring avoidable interference to the image acquisition.<\/span><\/p>\n

<\/span><\/p>\n

Other different cameras have similar pins and they're all the same.<\/span> Here are the hardware connections:<\/span><\/p>\n

<\/span><\/p>\n

1. Pay attention to line field interruption If the connection is correct, the first small light on the system board will flash once every second.<\/span><\/p>\n

<\/span><\/p>\n

How do I connect cables to ov7620? _ov7620 Hardware Connection<\/span><\/p>\n

\"\u753b\u50cf.png\"\/<\/span><\/p>\n

<\/span><\/p>\n

2. The vcc of the camera is connected to 5v power, gnd ground, do not connect wrong!<\/span><\/p>\n

<\/span><\/p>\n

3.<\/span> The core board leads ps0 to the rxd on the usb adapter and one is a common ground wire.<\/span> All right, you can see the image.<\/span><\/p>\n

<\/p>","protected":false},"excerpt":{"rendered":"

1. Function control of OV7620 The OV7620 is controlled using the SeriaICameraControlBus (SCCB) protocol. SCCB is a simplified I2C protocol, SIO-l is a serial clock input line, SIO-O is a serial bidirectional data line, respectively equivalent to SCL and SDA of I2C protocol. The bus timing of SCCB is basically the same as that of I2C, and its response signal ACK is called the 9th bit of a transmission unit, which is divided into Don't Care and NA. The Don 'tcare bit is generated by the slave machine. The NA bit is generated by the host. Since SCCB does not support multi-byte read and write, the NA bit must be high. In addition, SCCB has no concept of repeated start, so in the SCCB read cycle, the host must send the bus stop condition after sending the on-chip register address. Otherwise, the slave will not be able to generate a Don 'tCare response signal when the read command is sent. Due to some subtle differences between I2C and SCCB, the SCCB bus is simulated by GPIO. The pins connected to SCL are always set to output mode, while the pins connected to SDA dynamically change the input\/output mode of the pins during data transmission by setting the value of IODIR. The write cycle of SCCB directly uses the write cycle timing of I2C bus protocol. The SC-CB read cycle adds a bus stop condition. The addresses of the OV7620 function registers are 0x00 ~ 0x7C (many of them are reserved registers). By setting the corresponding registers, the OV7620 can be made to work in different modes. For example, to set OV7620 to continuous scanning and RGB raw data 16-bit output mode, you need to perform the following Settings: I2CSendByte () is a register write function, its first parameter OV7620 is the chip address 0x42 defined by the macro, the second parameter is the on-chip register address, and the third parameter is the corresponding register setting value. 2. OV7620 clock synchronization The OV7620 has four synchronization signals: VSYNC (vertical synchronization signal), FODD (odd-field synchronization signal), HSYNC (horizontal synchronization signal) and PCLK (pixel synchronization signal). When continuous scanning is adopted, only three synchronization signals, VSYNC, HSYNC and PCLK, are used, as shown in Figure l. The HREF level reference signal is also introduced to detect the effective size of the OV7620 scan window. The three external interrupt pins of the LPC2210 are used as inputs to the three synchronization signals, and the corresponding interrupt service programs are Vsync_IRQ (), Hsync_IRQ (), and Pclk_IRQ (). A two-dimensional array is defined in memory to store image data, and one dimension is represented by variable y, which is used for horizontal synchronization signal counting. Two dimensions are represented by variable x, which is used for pixel synchronization signal counting. The basic process of image acquisition is as follows: after OV7620 is initialized with SCCB, enable the corresponding interrupt of VSYNC, and determine whether a frame of data has been obtained in the interrupt service program of Vsync_IRQ (). If so, the data is processed in the cycle body of the main program. If not, enable the interrupt corresponding to HSYNC and set y to O. In the Hsync_IRQ () interrupt service program, determine the valid level of the HREF. If it is valid, y is increased by 1, x is set to O, and the interrupt corresponding to PCLK is enabled. In the Pclk_IRQ () interrupt service program, the valid level of the HREF is determined, and if it is valid, the z is increased, and the image data of a pixel is collected. 3, image data output speed matching Among the three synchronization signals of OV7620, PCLK has the shortest period. When the OV7620 uses a 27MHz system clock, the default PCLK cycle is 74ns. The interrupt response time of LPC2210 is much greater than this value. The maximum interrupt delay of LPC2210 is 27 processor instruction cycles, the minimum delay is 4 instruction cycles, plus the interrupt service time, the field recovery time, etc., the time to complete an interrupt response is greater than 7 to 30 instruction cycles. When the LPC2210 uses the maximum system frequency of 60MHz, its interrupt response time is much higher than that of O. 2 ~ 0, 6\u03bcs, so the PCLK of OV7620 can only be reduced. By setting the clock frequency control register, the period of PCLK can be set to about 4\u03bcs. 4. Access of image data When the OV7620 is operating in master device mode, its YUV channel will continuously output data to the bus. If the YUV channel of OV7620 is directly connected to the DO ~ D15 data bus of LPC2210, the data bus will be interfered with, so that LPC2210 can not run normally; If the method of using 74HC244 and other isolation and time-sharing data bus will greatly reduce the running speed of the system, so that LPC2210 can not take the data on the bus in time, resulting in incomplete image data. Since the data bus width of LPC2210 is 32 bits, and Flash and SRAM only occupy the low 16-bit data line D0 ~ D15, the method in Figure l can be used to set the idle high 16-bit data line D16 ~ D31 as GPIO for collecting the 16-bit image data output from OV7620. 5. Recovery of image data When OV7620 adopts 16-bit output mode, the data output formats of Y channel and UV channel are listed in Table l. As you can see from Table l, each row of Y channels and UV channels alternately outputs duplicate data from the previous row and new data from this row. Within a row, B data appears only in odd columns and R data appears only in even columns. The following takes a 5\u00d75 pixel lattice as an example to introduce the recovery of image data in detail. First, define a 5\u00d715 byte array to read 5\u00d75 pixel image data in Pclk_IRQ () interrupt service program; Then the<\/p>","protected":false},"author":5,"featured_media":11849,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_eb_attr":"","footnotes":""},"categories":[381],"tags":[394,376],"class_list":["post-11848","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-knowledge","tag-ov7620","tag-camera-module"],"_links":{"self":[{"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/posts\/11848","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/comments?post=11848"}],"version-history":[{"count":0,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/posts\/11848\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/media\/11849"}],"wp:attachment":[{"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/media?parent=11848"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/categories?post=11848"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgzx.hk\/ja\/wp-json\/wp\/v2\/tags?post=11848"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}