{"id":12972,"date":"2024-07-26T02:06:36","date_gmt":"2024-07-26T02:06:36","guid":{"rendered":"https:\/\/dgzx.hk?p=12972"},"modified":"2024-07-26T02:06:36","modified_gmt":"2024-07-26T02:06:36","slug":"scientific-grade-cmos-scmos-cameras-fundamentals","status":"publish","type":"post","link":"https:\/\/dgzx.hk\/vi\/may-anh-cmos-scmos-cap-khoa-hoc-co-ban\/","title":{"rendered":"M\u00e1y \u1ea3nh CMOS c\u1ea5p khoa h\u1ecdc (sCMOS): C\u01a1 b\u1ea3n"},"content":{"rendered":"

\"T\u1ea3i<\/p>\n

gi\u1edbi thi\u1ec7u<\/strong><\/span><\/p>\n

\u3000\u3000C\u1ea3m bi\u1ebfn b\u00e1n d\u1eabn oxit kim lo\u1ea1i b\u1ed5 sung (CMOS) l\u00e0 c\u00f4ng ngh\u1ec7 \u0111\u00e3 c\u00f3 t\u1eeb nh\u1eefng n\u0103m 1990. C\u00e1c m\u00e1y \u1ea3nh CMOS \u0111\u1ea7u ti\u00ean c\u1ea1nh tranh v\u1edbi c\u00f4ng ngh\u1ec7 CCD \u0111\u00e3 tr\u01b0\u1edfng th\u00e0nh h\u01a1n, nh\u01b0ng trong nh\u1eefng n\u0103m 1990 v\u00e0 \u0111\u1ea7u nh\u1eefng n\u0103m 2000, c\u00f4ng ngh\u1ec7 c\u1ea3m bi\u1ebfn CMOS \u0111\u00e3 \u0111\u01b0\u1ee3c c\u1ea3i thi\u1ec7n v\u00e0 c\u00f4ng ngh\u1ec7 CCD \u0111\u00e3 b\u1ecb v\u01b0\u1ee3t qua nh\u01b0 l\u00e0 c\u1ea3m bi\u1ebfn \u0111\u01b0\u1ee3c l\u1ef1a ch\u1ecdn cho m\u00e1y \u1ea3nh k\u1ef9 thu\u1eadt s\u1ed1 ti\u00eau d\u00f9ng. C\u00f4ng ngh\u1ec7 n\u00e0y sau \u0111\u00f3 \u0111\u00e3 \u0111\u01b0\u1ee3c c\u1ea3i ti\u1ebfn h\u01a1n n\u1eefa \u0111\u1ec3 \u0111\u00e1p \u1ee9ng c\u00e1c y\u00eau c\u1ea7u cao h\u01a1n c\u1ea7n thi\u1ebft cho h\u00ecnh \u1ea3nh khoa h\u1ecdc.<\/span><\/span><\/p>\n

C\u00f4ng ngh\u1ec7 c\u1ea3m bi\u1ebfn CMOS kh\u00e1c v\u1edbi c\u1ea3m bi\u1ebfn CCD \u1edf ch\u1ed7, thay v\u00ec \u0111\u01b0a t\u1ea5t c\u1ea3 c\u00e1c \u0111i\u1ec3m \u1ea3nh c\u1ea3m bi\u1ebfn qua m\u1ed9t n\u00fat \u0111\u1ea7u ra, m\u1ed9t b\u1ed9 khu\u1ebfch \u0111\u1ea1i v\u00e0 m\u1ed9t b\u1ed9 chuy\u1ec3n \u0111\u1ed5i t\u01b0\u01a1ng t\u1ef1 sang s\u1ed1 (ADC) nh\u01b0 trong c\u1ea3m bi\u1ebfn CCD, c\u1ea3m bi\u1ebfn CMOS c\u00f3 m\u1ed9t t\u1ee5 \u0111i\u1ec7n v\u00e0 b\u1ed9 khu\u1ebfch \u0111\u1ea1i thu nh\u1ecf tr\u00ean m\u1ed7i \u0111i\u1ec3m \u1ea3nh v\u00e0 m\u1ed9t ADC tr\u00ean m\u1ed7i c\u1ed9t (nh\u01b0 th\u1ec3 hi\u1ec7n trong H\u00ecnh 1). M\u1ed7i ADC ho\u1ea1t \u0111\u1ed9ng \u0111\u1ed3ng th\u1eddi, \u0111\u1ecdc to\u00e0n b\u1ed9 c\u1ed9t, thay v\u00ec m\u1ed9t \u0111i\u1ec3m \u1ea3nh ri\u00eang l\u1ebb c\u1ee7a to\u00e0n b\u1ed9 c\u1ea3m bi\u1ebfn. \u0110i\u1ec1u n\u00e0y l\u00e0m cho qu\u00e1 tr\u00ecnh nhanh h\u01a1n v\u00e0 y\u00eau c\u1ea7u \u00edt n\u0103ng l\u01b0\u1ee3ng h\u01a1n 100 l\u1ea7n so v\u1edbi ki\u1ebfn tr\u00fac c\u1ea3m bi\u1ebfn CCD.<\/span><\/p>\n

\"T\u1ea3i<\/p>\n

H\u00ecnh 1: So s\u00e1nh ki\u1ebfn tr\u00fac \u0111\u1ecdc c\u1ee7a c\u1ea3m bi\u1ebfn CCD truy\u1ec1n li\u00ean d\u00f2ng v\u00e0 c\u1ea3m bi\u1ebfn sCMOS. B\u00ean tr\u00e1i: \u0110\u1ecbnh d\u1ea1ng CCD truy\u1ec1n li\u00ean d\u00f2ng, trong \u0111\u00f3 c\u00e1c electron \u0111\u01b0\u1ee3c truy\u1ec1n t\u1eeb c\u1ea3m bi\u1ebfn \u0111\u1ebfn thanh ghi \u0111\u1ecdc, \u0111\u1ebfn m\u1ed9t n\u00fat \u0111\u1ea7u ra, \u0111\u01b0\u1ee3c khu\u1ebfch \u0111\u1ea1i (th\u00f4ng qua t\u1ee5 \u0111i\u1ec7n (C) v\u00e0 b\u1ed9 khu\u1ebfch \u0111\u1ea1i (A)) v\u00e0 \u0111\u01b0\u1ee3c chuy\u1ec3n \u0111\u1ed5i th\u00e0nh m\u1ee9c \u0111\u1ed9 x\u00e1m k\u1ef9 thu\u1eadt s\u1ed1 b\u1edfi m\u1ed9t ADC. Sau \u0111\u00f3, d\u1eef li\u1ec7u n\u00e0y \u0111\u01b0\u1ee3c g\u1eedi \u0111\u1ebfn m\u00e1y t\u00ednh. B\u00ean ph\u1ea3i: \u0110\u1ecbnh d\u1ea1ng CMOS th\u00f4ng th\u01b0\u1eddng, trong \u0111\u00f3 m\u1ed7i \u0111i\u1ec3m \u1ea3nh c\u00f3 m\u1ed9t t\u1ee5 \u0111i\u1ec7n v\u00e0 b\u1ed9 khu\u1ebfch \u0111\u1ea1i. \u0110i\u1ec1u n\u00e0y c\u00f3 ngh\u0129a l\u00e0 c\u00e1c photon chi\u1ebfu v\u00e0o t\u1eebng \u0111i\u1ec3m \u1ea3nh s\u1ebd t\u1ea1o ra c\u00e1c electron \u0111\u01b0\u1ee3c chuy\u1ec3n \u0111\u1ed5i th\u00e0nh \u0111i\u1ec7n \u00e1p c\u00f3 th\u1ec3 \u0111\u1ecdc \u0111\u01b0\u1ee3c tr\u00ean \u0111i\u1ec3m \u1ea3nh. \u0110i\u1ec7n \u00e1p t\u1eeb to\u00e0n b\u1ed9 c\u1ed9t \u0111\u01b0\u1ee3c g\u1eedi \u0111\u1ebfn m\u1ed9t ADC (m\u1ed7i c\u1ed9t c\u00f3 m\u1ed9t ADC), \u0111\u01b0\u1ee3c g\u1eedi tr\u1ef1c ti\u1ebfp \u0111\u1ebfn m\u00e1y t\u00ednh. \u0110i\u1ec1u n\u00e0y cho ph\u00e9p camera CMOS nhanh h\u01a1n nhi\u1ec1u v\u00ec ch\u00fang ho\u1ea1t \u0111\u1ed9ng song song.<\/span><\/p>\n

\u3000\u3000C\u00f4ng ngh\u1ec7 sCMOS<\/strong><\/span><\/p>\n

\u3000\u3000N\u0103m 2009, c\u00f4ng ngh\u1ec7 CMOS khoa h\u1ecdc (sCMOS) \u0111\u01b0\u1ee3c gi\u1edbi thi\u1ec7u v\u00e0 camera sCMOS \u0111\u00e3 c\u00f3 m\u1eb7t tr\u00ean th\u1ecb tr\u01b0\u1eddng v\u00e0o n\u0103m 2010-11. Camera sCMOS c\u00f3 \u0111\u1ed9 nhi\u1ec5u th\u1ea5p, t\u1ed1c \u0111\u1ed9 cao v\u00e0 tr\u01b0\u1eddng nh\u00ecn r\u1ed9ng, khi\u1ebfn ch\u00fang tr\u1edf n\u00ean l\u00fd t\u01b0\u1edfng cho nhi\u1ec1u \u1ee9ng d\u1ee5ng t\u1eeb thi\u00ean v\u0103n h\u1ecdc \u0111\u1ebfn k\u00ednh hi\u1ec3n vi.<\/span><\/span><\/p>\n

\u3000\u3000M\u00e0n tr\u1eadp l\u0103n v\u00e0 ch\u1ebf \u0111\u1ed9 to\u00e0n c\u1ea7u<\/strong><\/span><\/p>\n

\u3000\u3000C\u1ea3m bi\u1ebfn sCMOS kh\u00e1c v\u1edbi c\u1ea3m bi\u1ebfn CCD \u1edf ch\u1ed7 ch\u00fang th\u01b0\u1eddng c\u00f3 m\u00e0n tr\u1eadp l\u0103n. Vi\u1ec7c thu th\u1eadp h\u00ecnh \u1ea3nh b\u1eaft \u0111\u1ea7u t\u1eeb ph\u00eda tr\u00ean c\u00f9ng c\u1ee7a c\u1ea3m bi\u1ebfn v\u00e0 ho\u1ea1t \u0111\u1ed9ng theo t\u1eebng d\u00f2ng. \u0110i\u1ec1u n\u00e0y cho ph\u00e9p c\u1ea3m bi\u1ebfn thu th\u1eadp h\u00ecnh \u1ea3nh \u1edf t\u1ed1c \u0111\u1ed9 khung h\u00ecnh cao h\u01a1n v\u00e0 v\u1edbi \u0111\u1ed9 nhi\u1ec5u \u0111\u1ecdc th\u1ea5p h\u01a1n. T\u1ed1c \u0111\u1ed9 c\u1ee7a m\u00e1y \u1ea3nh sCMOS li\u00ean quan tr\u1ef1c ti\u1ebfp \u0111\u1ebfn s\u1ed1 d\u00f2ng v\u00e0 th\u1eddi gian d\u00f2ng, l\u00e0 th\u1eddi gian gi\u1eefa vi\u1ec7c thu th\u1eadp m\u1ed9t d\u00f2ng v\u00e0 d\u00f2ng kh\u00e1c.<\/span><\/span><\/p>\n

M\u00e0n tr\u1eadp l\u0103n "m\u1edf" v\u00e0 "\u0111\u00f3ng" b\u1eb1ng c\u00e1ch x\u00f3a \u0111i\u1ec7n t\u00edch \u0111\u00e3 c\u00f3 trong m\u1ed9t h\u00e0ng v\u00e0 \u0111o b\u1ea5t k\u1ef3 photon m\u1edbi n\u00e0o \u0111i v\u00e0o. \u0110i\u1ec1u n\u00e0y cho ph\u00e9p x\u1ea3y ra s\u1ef1 ch\u1ed3ng ch\u00e9o gi\u1eefa h\u00e0ng pixel hi\u1ec7n t\u1ea1i trong khung h\u00ecnh thu \u0111\u01b0\u1ee3c (h\u00ecnh \u1ea3nh \u0111ang \u0111\u01b0\u1ee3c thu \u0111\u01b0\u1ee3c) v\u00e0 h\u00e0ng pixel th\u1ea5p h\u01a1n trong khung h\u00ecnh tr\u01b0\u1edbc \u0111\u00f3 (h\u00ecnh \u1ea3nh \u0111ang \u0111\u01b0\u1ee3c \u0111\u1ecdc ra) (H\u00ecnh 2).<\/span><\/p>\n

\"T\u1ea3i<\/p>\n

H\u00ecnh 2: S\u01a1 \u0111\u1ed3 bi\u1ec3u th\u1ecb c\u00e1ch thu th\u1eadp khung h\u00ecnh ch\u1ed3ng l\u00ean vi\u1ec7c \u0111\u1ecdc khung h\u00ecnh tr\u01b0\u1edbc \u0111\u00f3. \u0110i\u1ec1u n\u00e0y cho ph\u00e9p sCMOS thu th\u1eadp v\u00e0 \u0111\u1ecdc nhanh.<\/span><\/p>\n

M\u1ed9t s\u1ed1 c\u1ea3m bi\u1ebfn sCMOS c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng trong ch\u1ebf \u0111\u1ed9 m\u00e0n tr\u1eadp gi\u1ea3 to\u00e0n c\u1ee5c \u0111\u1ec3 \u0111\u1ea1t \u0111\u01b0\u1ee3c \u0111\u1ed9 m\u00e9o b\u1eb1ng kh\u00f4ng v\u00e0 cho ph\u00e9p c\u00e1c \u1ee9ng d\u1ee5ng li\u00ean quan \u0111\u1ebfn thay \u0111\u1ed5i ph\u1ea7n c\u1ee9ng gi\u1eefa c\u00e1c khung h\u00ecnh, ch\u1eb3ng h\u1ea1n nh\u01b0 thu th\u1eadp k\u00eanh \u0111\u00f4i tu\u1ea7n t\u1ef1. M\u00e0n tr\u1eadp gi\u1ea3 to\u00e0n c\u1ee5c n\u00e0y t\u1eadn d\u1ee5ng l\u1ee3i th\u1ebf c\u1ee7a vi\u1ec7c ki\u1ec3m so\u00e1t k\u00edch ho\u1ea1t ngu\u1ed3n s\u00e1ng. \u0110\u1ec3 t\u1ea1o m\u00e0n tr\u1eadp to\u00e0n c\u1ee5c n\u00e0y, m\u00e1y \u1ea3nh c\u1ea7n k\u00edch ho\u1ea1t m\u00e0n tr\u1eadp l\u0103n trong \u0111i\u1ec1u ki\u1ec7n t\u1ed1i. Sau \u0111\u00f3, b\u1eb1ng c\u00e1ch k\u00edch ho\u1ea1t ngu\u1ed3n s\u00e1ng v\u00e0 d\u1eebng \u00e1nh s\u00e1ng c\u00f9ng l\u00fac v\u1edbi vi\u1ec7c d\u1eebng m\u00e1y \u1ea3nh, m\u1ed9t khu v\u1ef1c c\u1ee7a m\u1ea3ng c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c chi\u1ebfu s\u00e1ng c\u00f9ng l\u00fac, gi\u1ed1ng nh\u01b0 m\u00e0n tr\u1eadp to\u00e0n c\u1ee5c (nh\u01b0 th\u1ec3 hi\u1ec7n trong H\u00ecnh 3).<\/span><\/p>\n

\"T\u1ea3i<\/p>\n

H\u00ecnh 3: Ba \u0111\u1ecbnh d\u1ea1ng m\u00e0n tr\u1eadp ch\u00ednh. H\u1ea7u h\u1ebft CCD\/EMCC \u0111\u1ec1u c\u00f3 m\u00e0n tr\u1eadp to\u00e0n c\u1ee5c th\u1ef1c s\u1ef1, cho ph\u00e9p t\u1ea5t c\u1ea3 c\u00e1c \u0111i\u1ec3m \u1ea3nh \u0111\u01b0\u1ee3c \u0111\u1ecdc \u0111\u1ed3ng th\u1eddi khi ch\u00fang ti\u1ebfp x\u00fac v\u1edbi \u00e1nh s\u00e1ng. H\u1ea7u h\u1ebft c\u00e1c c\u1ea3m bi\u1ebfn sCMOS \u0111\u1ec1u c\u00f3 m\u00e0n tr\u1eadp l\u0103n, m\u1eb7c d\u00f9 nhanh v\u00e0 nh\u1ea1y (t\u1eeb c\u1ea3m bi\u1ebfn chi\u1ebfu s\u00e1ng ng\u01b0\u1ee3c), nh\u01b0ng c\u00f3 th\u1ec3 t\u1ea1o ra hi\u1ec7n t\u01b0\u1ee3ng nhi\u1ec5u. M\u00e0n tr\u1eadp to\u00e0n c\u1ee5c gi\u1ea3 s\u1eed d\u1ee5ng m\u1ed9t b\u1ed9 k\u00edch ho\u1ea1t \u0111\u1ec3 \u0111i\u1ec1u khi\u1ec3n ngu\u1ed3n s\u00e1ng, cho ph\u00e9p m\u00e0n tr\u1eadp to\u00e0n c\u1ee5c \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng trong m\u00e0n tr\u1eadp l\u0103n (n\u1ebfu \u0111\u01b0\u1ee3c \u0111\u1ecbnh th\u1eddi gian ch\u00ednh x\u00e1c).<\/span><\/p>\n

\u3000\u3000So s\u00e1nh gi\u1eefa CCD v\u00e0 sCMOS<\/strong><\/span><\/p>\n

S\u1ef1 kh\u00e1c bi\u1ec7t gi\u1eefa ki\u1ebfn tr\u00fac c\u1ea3m bi\u1ebfn CCD v\u00e0 sCMOS c\u00f3 c\u1ea3 \u01b0u \u0111i\u1ec3m v\u00e0 nh\u01b0\u1ee3c \u0111i\u1ec3m. M\u1ed9t s\u1ed1 \u01b0u \u0111i\u1ec3m c\u1ee7a c\u00f4ng ngh\u1ec7 sCMOS so v\u1edbi c\u00f4ng ngh\u1ec7 CCD nh\u01b0 sau:<\/span><\/p>\n

1. \u0110\u1ed9 nhi\u1ec5u \u0111\u1ecdc th\u1ea5p: sCMOS c\u00f3 \u0111\u1ed9 nhi\u1ec5u \u0111\u1ecdc l\u00e0 ~1 e-, trong khi CCD c\u00f3 \u0111\u1ed9 nhi\u1ec5u \u0111\u1ecdc l\u00e0 5-6 e-. \u0110\u1ec3 t\u00ecm hi\u1ec3u v\u1ec1 vai tr\u00f2 c\u1ee7a \u0111\u1ed9 nhi\u1ec5u \u0111\u1ecdc gi\u1ea3m v\u00e0 \u0111\u1ed9 nh\u1ea1y t\u0103ng, h\u00e3y nh\u1ea5p v\u00e0o \u0111\u00e2y.<\/span><\/p>\n

2. T\u1ed1c \u0111\u1ed9 cao: sCMOS c\u00f3 th\u1ec3 \u0111\u1ea1t t\u1edbi 100 fps, trong khi CCD l\u00e0 ~20 fps. \u0110i\u1ec1u n\u00e0y l\u00e0 do m\u1ed7i c\u1ed9t c\u00f3 m\u1ed9t ADC li\u00ean quan, do \u0111\u00f3 ch\u1ec9 c\u1ea7n x\u1eed l\u00fd m\u1ed9t ph\u1ea7n nh\u1ecf d\u1eef li\u1ec7u.<\/span><\/p>\n

3. Tr\u01b0\u1eddng nh\u00ecn r\u1ed9ng: C\u1ea3m bi\u1ebfn sCMOS c\u00f3 ph\u1ea1m vi \u0111\u01b0\u1eddng ch\u00e9o l\u00e0 19-29 mm, trong khi CCD c\u00f3 ph\u1ea1m vi \u0111\u01b0\u1eddng ch\u00e9o l\u00e0 11-16 mm<\/span><\/p>\n

4. Hi\u1ec7u su\u1ea5t n\u0103ng l\u01b0\u1ee3ng: Do song song h\u00f3a, sCMOS ti\u00eau th\u1ee5 \u00edt \u0111i\u1ec7n n\u0103ng h\u01a1n 100 l\u1ea7n so v\u1edbi CCD<\/span><\/p>\n

M\u1eb7c d\u00f9 c\u00f4ng ngh\u1ec7 sCMOS v\u01b0\u1ee3t tr\u1ed9i h\u01a1n c\u00f4ng ngh\u1ec7 CCD \u1edf nhi\u1ec1u kh\u00eda c\u1ea1nh, nh\u01b0ng n\u00f3 v\u1eabn c\u00f3 m\u1ed9t s\u1ed1 nh\u01b0\u1ee3c \u0111i\u1ec3m:<\/span><\/p>\n

T\u0103ng nhi\u1ec5u m\u1eabu c\u1ed1 \u0111\u1ecbnh v\u00e0 th\u1eddi gian: Khi t\u1eebng \u0111i\u1ec3m \u1ea3nh \u0111\u01b0\u1ee3c \u0111\u1ecdc ri\u00eang l\u1ebb, nhi\u1ec5u m\u1eabu c\u1ed1 \u0111\u1ecbnh v\u00e0 th\u1eddi gian t\u0103ng l\u00ean. C\u1ea3m bi\u1ebfn sCMOS c\u00f3 di\u1ec7n t\u00edch \u0111\u1ecdc ho\u1ea1t \u0111\u1ed9ng l\u1edbn h\u01a1n so v\u1edbi CCD, d\u1eabn \u0111\u1ebfn t\u0103ng c\u00e1c ngu\u1ed3n nhi\u1ec5u n\u00e0y. \u0110i\u1ec1u n\u00e0y c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c gi\u1ea3m b\u1edbt b\u1eb1ng c\u00e1ch thi\u1ebft k\u1ebf \u0111i\u1ec7n t\u1eed c\u1ea9n th\u1eadn v\u00e0 hi\u1ec7u chu\u1ea9n c\u1ee7a c\u00f4ng ty m\u00e1y \u1ea3nh.<\/span><\/p>\n

C\u00e1c hi\u1ec7n t\u01b0\u1ee3ng nhi\u1ec5u m\u00e0n tr\u1eadp l\u0103n: C\u1ea3m bi\u1ebfn sCMOS c\u00f3 th\u1ec3 s\u1eed d\u1ee5ng m\u00e0n tr\u1eadp l\u0103n \u0111\u1ec3 thu \u0111\u01b0\u1ee3c h\u00ecnh \u1ea3nh, nh\u01b0ng n\u1ebfu c\u00e1c v\u1eadt th\u1ec3 \u0111\u1ed9ng trong h\u00ecnh \u1ea3nh \u0111\u1ee7 nhanh \u0111\u1ec3 di chuy\u1ec3n theo thang th\u1eddi gian t\u01b0\u01a1ng t\u1ef1 nh\u01b0 m\u00e0n tr\u1eadp l\u0103n, c\u00f3 th\u1ec3 xu\u1ea5t hi\u1ec7n hi\u1ec7u \u1ee9ng m\u00e9o h\u00ecnh. C\u00e1c ph\u00e9p \u0111\u1ecdc l\u1ec7ch gi\u1eefa c\u00e1c h\u00e0ng tr\u00ean c\u00f9ng v\u00e0 d\u01b0\u1edbi c\u00f9ng c\u1ee7a c\u1ea3m bi\u1ebfn c\u0169ng c\u00f3 th\u1ec3 g\u00e2y ra hi\u1ec7n t\u01b0\u1ee3ng nhi\u1ec5u h\u00ecnh \u1ea3nh v\u00e0 m\u1ea5t th\u00f4ng tin, \u0111\u1ed3ng th\u1eddi l\u00e0m t\u0103ng \u0111\u00e1ng k\u1ec3 th\u1eddi gian ph\u01a1i s\u00e1ng t\u1ed1i thi\u1ec3u hi\u1ec7u qu\u1ea3 cho m\u1ed9t s\u1ed1 \u1ee9ng d\u1ee5ng.<\/span><\/p>\n

\u3000\u3000sCMOS chi\u1ebfu s\u00e1ng ng\u01b0\u1ee3c<\/strong><\/span><\/p>\n

\u3000\u3000M\u1ed9t s\u1ed1 c\u1ea3m bi\u1ebfn sCMOS \u0111\u1eddi \u0111\u1ea7u c\u00f3 v\u1ea5n \u0111\u1ec1 v\u1ec1 ch\u1ea5t l\u01b0\u1ee3ng n\u1ec1n v\u00e0 nhi\u1ec5u, h\u1ea1n ch\u1ebf vi\u1ec7c s\u1eed d\u1ee5ng CMOS trong c\u00e1c \u1ee9ng d\u1ee5ng \u0111\u00f2i h\u1ecfi kh\u1eaft khe h\u01a1n. \u0110\u1ec3 kh\u1eafc ph\u1ee5c v\u1ea5n \u0111\u1ec1 n\u00e0y, c\u00f4ng ngh\u1ec7 c\u1ea7n \u0111\u01b0\u1ee3c c\u1ea3i thi\u1ec7n v\u1edbi \u0111\u1ed9 nh\u1ea1y cao h\u01a1n. N\u0103m 2016, sCMOS chi\u1ebfu s\u00e1ng ng\u01b0\u1ee3c \u0111\u00e3 \u0111\u01b0\u1ee3c gi\u1edbi thi\u1ec7u, cung c\u1ea5p hi\u1ec7u su\u1ea5t l\u01b0\u1ee3ng t\u1eed \u0111\u1ec9nh (QE) 95% m\u00e0 kh\u00f4ng \u1ea3nh h\u01b0\u1edfng \u0111\u1ebfn k\u00edch th\u01b0\u1edbc \u0111i\u1ec3m \u1ea3nh, \u0111\u1ed3ng th\u1eddi c\u0169ng c\u1ea3i thi\u1ec7n ch\u1ea5t l\u01b0\u1ee3ng n\u1ec1n. H\u00ecnh 4 cho th\u1ea5y s\u01a1 \u0111\u1ed3 c\u00f4ng ngh\u1ec7 sCMOS chi\u1ebfu s\u00e1ng ng\u01b0\u1ee3c, c\u00f9ng v\u1edbi \u0111\u01b0\u1eddng cong QE cho th\u1ea5y s\u1ef1 kh\u00e1c bi\u1ec7t gi\u1eefa sCMOS \u0111\u1eddi \u0111\u1ea7u v\u00e0 sCMOS chi\u1ebfu s\u00e1ng ng\u01b0\u1ee3c.<\/span><\/span><\/p>\n


<\/span><\/p>\n

\"T\u1ea3i<\/p>\n

<\/p>\n

H\u00ecnh 4: C\u00f4ng ngh\u1ec7 sCMOS chi\u1ebfu s\u00e1ng ph\u00eda tr\u01b0\u1edbc so v\u1edbi c\u00f4ng ngh\u1ec7 sCMOS chi\u1ebfu s\u00e1ng ph\u00eda sau. Tr\u00ean: C\u1ea3m bi\u1ebfn chi\u1ebfu s\u00e1ng ph\u00eda tr\u01b0\u1edbc (tr\u00e1i) c\u00f3 QE th\u1ea5p h\u01a1n v\u00ec \u00e1nh s\u00e1ng b\u1ecb ph\u00e2n t\u00e1n trong c\u00e1c \u0111i\u1ec3m \u1ea3nh v\u00e0 d\u00e2y c\u1ea3m bi\u1ebfn tr\u01b0\u1edbc khi chi\u1ebfu v\u00e0o ch\u1ea5t n\u1ec1n silicon. Trong c\u1ea3m bi\u1ebfn chi\u1ebfu s\u00e1ng ph\u00eda sau (ph\u1ea3i), \u00e1nh s\u00e1ng chi\u1ebfu tr\u1ef1c ti\u1ebfp v\u00e0o c\u1ea3m bi\u1ebfn, t\u1ea1o ra QE cao h\u01a1n. D\u01b0\u1edbi: So s\u00e1nh c\u00e1c \u0111\u01b0\u1eddng cong QE cho nhi\u1ec1u c\u00f4ng ngh\u1ec7 sCMOS chi\u1ebfu s\u00e1ng ph\u00eda tr\u01b0\u1edbc kh\u00e1c nhau (s\u1edbm, sCMOS 72% v\u00e0 82%) so v\u1edbi c\u00f4ng ngh\u1ec7 sCMOS chi\u1ebfu s\u00e1ng ph\u00eda sau (QE c\u1ee7a KURO \u0111\u1ea1t \u0111\u1ec9nh \u1edf 95%).<\/span><\/p>\n

\u3000\u3000T\u00f3m t\u1eaft<\/strong><\/span><\/p>\n

\u3000\u3000C\u1ea3m bi\u1ebfn sCMOS t\u1eadn d\u1ee5ng l\u1ee3i th\u1ebf c\u1ee7a vi\u1ec7c t\u00edch h\u1ee3p m\u1ea1ch ho\u1ea1t \u0111\u1ed9ng v\u00e0o t\u1eebng \u0111i\u1ec3m \u1ea3nh. \u0110i\u1ec1u n\u00e0y cho ph\u00e9p \u0111\u1ecdc t\u1eebng \u0111i\u1ec3m \u1ea3nh ri\u00eang l\u1ebb. M\u1ed9t b\u1ed9 chuy\u1ec3n \u0111\u1ed5i analog sang k\u1ef9 thu\u1eadt s\u1ed1 c\u0169ng \u0111\u01b0\u1ee3c g\u1eafn v\u00e0o t\u1eebng c\u1ed9t, cho ph\u00e9p t\u1ed1c \u0111\u1ed9 khung h\u00ecnh cao h\u01a1n trong khi v\u1eabn duy tr\u00ec \u0111\u1ed9 nhi\u1ec5u \u0111\u1ecdc th\u1ea5p, tr\u01b0\u1eddng nh\u00ecn r\u1ed9ng v\u00e0 hi\u1ec7u su\u1ea5t n\u0103ng l\u01b0\u1ee3ng cao.<\/span><\/span><\/p>\n

M\u1eb7c d\u00f9 nhi\u1ec5u th\u1eddi gian v\u00e0 nhi\u1ec5u m\u1eabu c\u1ed1 \u0111\u1ecbnh t\u0103ng l\u00ean do s\u1ed1 l\u01b0\u1ee3ng m\u1ea1ch ho\u1ea1t \u0111\u1ed9ng tr\u00ean c\u1ea3m bi\u1ebfn t\u0103ng l\u00ean, c\u00f4ng ngh\u1ec7 sCMOS v\u1eabn c\u00f3 nhi\u1ec1u \u01b0u \u0111i\u1ec3m trong nhi\u1ec1u \u1ee9ng d\u1ee5ng.<\/span><\/p>\n

<\/p>","protected":false},"excerpt":{"rendered":"

introduce \u3000\u3000Complementary Metal Oxide Semiconductor (CMOS) sensors are a technology that has been around since the 1990s. Early CMOS cameras were competing with the more mature CCD technology, but during the 1990s and early 2000s, CMOS sensor technology improved and CCD technology was surpassed as the sensor of choice for consumer digital cameras. The technology was subsequently further improved to meet the higher requirements necessary for scientific imaging. \u3000\u3000CMOS sensor technology differs from CCD sensors in that, instead of feeding all sensor pixels through one output node, one amplifier, and one analog-to-digital converter (ADC) as in CCD sensors, CMOS sensors have a miniaturized capacitor and amplifier on each pixel, and one ADC on each column (as shown in Figure 1). Each ADC works simultaneously, reading out the entire column, rather than a single pixel of the entire sensor. This makes the process faster and requires 100 times less power than the CCD sensor architecture. Figure 1: Comparing the readout architectures of interline transfer CCD and sCMOS sensors. Left: Interline transfer CCD format, where electrons are transferred from the sensor to a readout register, to an output node, amplified (via a capacitor (C) and amplifier (A)), and converted to digital grayscale levels by an ADC. This is then sent to a computer. Right: A typical CMOS format, where each pixel has a capacitor and amplifier. This means that photons that hit each pixel create electrons that are converted to a readable voltage across the pixel. The voltages from the entire column are sent to an ADC (of which there is one per column), which is sent directly to a computer. This allows CMOS cameras to be much faster as they work in parallel. \u3000\u3000sCMOS Technology \u3000\u3000In 2009, scientific CMOS (sCMOS) technology was introduced, and sCMOS cameras became available in 2010-11. sCMOS cameras offer low noise, high speed, and a large field of view, making them ideal for a wide range of applications from astronomy to microscopy. \u3000\u3000Rolling Shutter and Global Mode \u3000\u3000sCMOS sensors differ from CCD sensors in that they typically have a rolling shutter. Image acquisition starts at the top of the sensor and works its way down line by line. This allows the sensor to acquire images at higher frame rates and with lower read noise. The speed of an sCMOS camera is directly related to the number of lines and the line time, which is the time between acquiring one line and another. \u3000\u3000The rolling shutter "opens" and "closes" by clearing the charge already within a row and measuring any new incoming photons. This allows overlap to occur between the current row of pixels in the acquired frame (the image being acquired) and the lower row of pixels in the previous frame (the image being read out) (Figure 2). Figure 2: Schematic diagram indicating how the acquisition of a frame overlaps with the readout of the previous frame. This enables sCMOS to have fast acquisition and readout. \u3000\u3000Some sCMOS sensors can be used in a pseudo-global shutter mode to achieve zero distortion and enable applications involving hardware changes between frames, such as sequential dual-channel acquisition. This pseudo-global shutter takes advantage of the control of the light source triggering. To create this global shutter, the camera needs to activate the rolling shutter in dark conditions. Then, by triggering the light source and stopping the light at the same time as stopping the camera, an area of the array can be illuminated at the same time, just like a global shutter (as shown in Figure 3). Figure 3: The three main shutter formats. Most CCD\/EMCCs have a true global shutter, which allows all pixels to be read simultaneously when they are exposed to light. Most sCMOS sensors have a rolling shutter, which, while fast and sensitive (from a back-illuminated sensor), can produce artifacts. A pseudo-global shutter uses a trigger to control the light source, allowing a global shutter to be used within a rolling shutter (if timed precisely). \u3000\u3000Comparison between CCD and sCMOS \u3000\u3000The differences in CCD and sCMOS sensor architectures have both advantages and disadvantages. Some of the advantages of sCMOS technology over CCD technology are as follows: \u3000\u30001. Low read noise: sCMOS has a read noise of ~1 e-, while CCD has a read noise of 5-6 e-. To learn about the role of reduced read noise and increased sensitivity, click here. \u3000\u30002. High speed: sCMOS can reach up to 100s fps, while CCD is ~20 fps. This is because each column has an associated ADC, so a small portion of the data needs to be processed. \u3000\u30003. Large field of view: sCMOS sensors have a diagonal range of 19-29 mm, while CCDs have a diagonal range of 11-16 mm \u3000\u30004. Power efficiency: Due to parallelization, sCMOS consumes 100 times less power than CCD \u3000\u3000While sCMOS technology is superior to CCD technology in many ways, it does have some disadvantages: \u3000\u3000Increased temporal and fixed pattern noise: When each pixel is read out individually, more temporal and fixed pattern noise is introduced. sCMOS sensors have more active readout area compared to CCDs, which leads to an increase in these noise sources. This can be reduced by careful electronic design and calibration by the camera company. \u3000\u3000Rolling shutter artifacts: sCMOS sensors can use a rolling shutter to acquire images, but if dynamic objects in the image are fast enough to move on a similar time scale as the rolling shutter, distortion effects can be introduced. Staggered readouts between the top and bottom rows of the sensor can also cause image artifacts and information loss, and significantly increase the effective minimum exposure time for some applications. \u3000\u3000Back-illuminated sCMOS \u3000\u3000Some early sCMOS sensors had background quality and noise issues, limiting the use of CMOS in more demanding applications. To overcome this issue, the technology needed to be improved with higher sensitivity. In 2016, back-illuminated sCMOS was introduced, offering 95% peak quantum efficiency (QE) without compromising pixel size, while also improving background quality. Figure 4 shows a schematic of back-illuminated sCMOS technology,<\/p>","protected":false},"author":5,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_eb_attr":"","footnotes":""},"categories":[1],"tags":[],"class_list":["post-12972","post","type-post","status-publish","format-standard","hentry","category-news"],"_links":{"self":[{"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/posts\/12972","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/comments?post=12972"}],"version-history":[{"count":0,"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/posts\/12972\/revisions"}],"wp:attachment":[{"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/media?parent=12972"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/categories?post=12972"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/dgzx.hk\/vi\/wp-json\/wp\/v2\/tags?post=12972"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}